FROMLIST: arm64: dts: qcom: Fix PCIe wake GPIO polarity#799
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The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-1-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-2-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-3-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-4-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-5-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-6-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-7-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-8-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-9-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-10-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-11-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-13-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-14-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-15-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-16-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-17-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20260611-wake-v2-18-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcieport0 and pcieport1. Add the missing pcieport1 label to the pcie1 root port node to allow board-level overrides. Move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/ &pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-19-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, and perst-gpios from the controller to pcie0_port0, adding a label to this node to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-20-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, adding a label to this node to allow board-level overrides. Move perst-gpios from the &pcie controller override to &pcie0_port0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-21-2744251b1181@oss.qualcomm.com/
The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/&pcie1_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-22-2744251b1181@oss.qualcomm.com/
The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a, &pcie3a, &pcie3b, and &pcie4 controller overrides to the respective &pcie2a_port0, &pcie3a_port0, &pcie3b_port0, and &pcie4_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-23-2744251b1181@oss.qualcomm.com/
The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a and &pcie3a controller overrides to the respective &pcie2a_port0 and &pcie3a_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-24-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the &pcie0 controller override to &pcieport0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-25-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-26-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcie2a_port0, pcie2b_port0, pcie3a_port0, pcie3b_port0, and pcie4_port0 nodes. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-27-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-28-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-29-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-30-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-31-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-32-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-33-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie_port0, and move perst-gpios/wake-gpios from the &pcie controller overrides to the &pcie_port0 node in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-34-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-35-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per-root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie0_port and pcie1_port0, and move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcie0_port/&pcie1_port0 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-36-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260611-wake-v2-37-2744251b1181@oss.qualcomm.com/
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PR #799 — validate-patchPR: #799
Final Summary
Recommendation:
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PR #799 — checker-log-analyzerPR: #799
Detailed report: Full report
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Fix PCIe wake GPIO polarity across multiple Qualcomm SoC DTS files.
PCIe WAKE# is an active-low signal per the PCIe specification, but many
DTS files incorrectly specify it as GPIO_ACTIVE_HIGH. This series fixes
the polarity to GPIO_ACTIVE_LOW for all affected platforms, and also
moves PCIe PHY and GPIO definitions to the correct PCIe port nodes.
Platforms fixed: sdx55, msm8996, sdm845, sc8180x, sm8150, sm8250,
sm8350, sm8450, sm8550, sm8650, sm8750, kaanapali, sar2130p, monaco,
lemans, sa8540p, kodiak, talos, msm8998, qcs404, qcs8550, sa8295p,
sa8540p, sc8280xp, sc8280xp, sdm845, sm8150, sm8250, sm8350, sm8450,
sm8550, sm8650, kodiak, msm8996.
Signed-off-by: Krishna Chaitanya Chundru krishna.chundru@oss.qualcomm.com
Link: https://lore.kernel.org/all/5a65ea59-b38d-4cc0-901a-01c239381d91@oss.qualcomm.com/